In semi-conductor manufacturing, after a plurality of chips are formed on a wafer, each of the chips are probed in sequence to initially check certain of their electrical characteristics. Following this initial probing the wafer is diced. Subsequent to the dicing operation the chips are packaged and subjected to a burn-in or acceleration test to remove those products subject to initial failure. This acceleration test simulates long-time operation by operating a circuit at a temperature of about 150.degree. C. while selected signal patterns and sequences are applied thereto.
One type of probe, used in the prior art, is comprised of a plurality of fixed needles mounted on respective cantilevered tungsten wires supported on an epoxy substrate. The wires are connected to an external tester and the needles are brought into to contact with respective ones of the chip input/output (I/O) pads. The needles thus serve as contact electrodes. This needle and cantilevered wire arrangement, although used for many years in the semi-conductor industry, is not suitable for high density products. Also it has been found that when the chip, under test, is heated during burn-in test the needles tend to shift, from their original positions, due to thermal expansion differences between the needles, the cantilevered wires and the chip. This thermal shifting is especially exaggerated when the chips are being tested in wafer, i.e., un-diced form and can cause false reading or inputs.
Recently multi-chip module technology (MCM), in which there are a plurality of chips mounted on a single package substrate, has been on the rise. The package used in this MCM technology is very expensive and may be lost if any chip thereon fails during acceleration testing. Therefore, if costs are to be reduced, means must be found that will enable the chips to be subjected to burn-in tests before they are packaged. One Solution is to subject the chips to acceleration testing while they are still in wafer form and prior to their dicing and packaging.
One attempt to meet the new requirements of the MCM technology, formed probe contact electrodes on the surface of a glass board by a lithographic technique with each contact being electrically connected to an external tester via a respective conductive via passing through a hole on the board. This was disclosed by T. Tada et al., in "A Fine Pitch Probe Technology" 1990 International Test Conference, pp. 900-906. Probes, so formed, were found to be unacceptable for they failed to compensate for differences in height between the I/O pads on the chip or wafer being tested. In such a case, some pads were not contacted by the contact electrodes because the glass, lacked sufficient flexibility. Moreover, the process to manufacture was found to be complicated and costly.
In an attempt to over come the flexibility problem, B. Leslie, et al., described, in an article entitled "Membrane Probe Card Technology for VLSI Wafer Testing" which was given at the 1988 International Test Conference, pp. 601-607, a new probe in which both the contact electrodes and interconnecting wiring were formed on a flexible film. It was believed that by applying pressure from a side opposite to the contact electrodes improved contact between a pad and a probe would be achieved. A similar device was disclosed in an article by M. Beiley, et al.; entitled "Array Probe Card," Multi-Chip Module Conference, pp. 28-31, 1992 and in U.S. Pat. No. 5,103,557 by G. J. Leedy, et al.
However, the probes, described in these articles, were found to also have contact electrode pressure problems. It was found that uniform contact electrode pressure on the pads could not be made due to the excessive flexibility of the entire film.
Thus, there exists a need for a probe which overcomes the contact electrode problems encountered by the prior art and which can be made inexpensively by an easily implemented process. Furthermore the probe is suitable for full wafer probing by providing a multiplicity of probes on a single substrate wherein each individual probe is provided for each respective chip location on the wafer.